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\title[fpgas] % (optional, only for long titles)
{Interconnect for commodity FPGA clusters}
\subtitle{standardized or customized?*}
\author[n. lastname, A. Theodore Markettos, P. J. Fox, S. W. Moore, A. W. Moore] % (optional, for multiple authors)
{n.~lastname\inst{1}}
\institute[Universities Here and There] % (optional)
{
  \inst{1}%
  institute\newline
  university
}
\date[SRAW 2022] % (optional)
{Scientific Research and Writing, 2022}
\subject{Computer Engineering}

\begin{document}
    % SLIDE 1
    \begin{frame}\titlepage\end{frame}
    % SLIDE 2
    \begin{frame}
*This presentation is about a rewriting/extension of A. Theodore Markettos, P. J. Fox, S. W. Moore, A. W. Moore, "Interconnect for comodity FPGA clusters: standardized or customized?", \textit{2014 24th International Conference on Field Programmable Logic and Applications (FPL)}, 2014, pp. 1-8. It has been written in the course of the seminar "Scientific Writing" (193.052) at TU Vienna, which shall help undergraduate students to get first experience in the art of scientific writing.
    \end{frame}
    % SLIDE 3
    \begin{frame}
        \frametitle{Problem}
        neural computation engine using an FPGA cluster:
        \newline
        \begin{itemize}
            \item{$10^{11}$ neurons with $10^{14}$ synaptic connections}
            \item{frequency of $10$ Hz means $10^{15}$ synaptic messages per second}
        \end{itemize}
        %Content goes here
    \end{frame}
    % SLIDE 4
    \begin{frame}
        \begin{columns}[c]
            \begin{column}{.75\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=\columnwidth]{res/bluelink-bluehive-machine.png}
                        \caption{a field-programmable custom computing machine for extreme-scale real-time neural network simulation}
                        \label{fig:bluehive-summary}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    % SLIDE 5
    \begin{frame}
        \frametitle{Problem}
        neural computation engine using an FPGA cluster, more specifically:
        \newline
        \begin{itemize}
            \item{Izhikevich neuron model}
            \item{48 bits per synaptic message}
            \item{128K neurons per FPGA}
            \newline
        \end{itemize}
        1.28M 48-bit synaptic messages per FPGA every millisecond!
        %Content goes here
    \end{frame}
    % SLIDE 6
    \begin{frame}
        \frametitle{Interconnect Requirements}
        \begin{itemize}
            \item{small message sizes (32-256 bits)}
            \item{low latency}
            \item{reliable}
            \item{hardware-only}
            \item{lightweight}
            \item{ubiquitous}
            \item{interoperable}
        \end{itemize}
    \end{frame}
    % SLIDE 7
    \begin{frame}
        \begin{columns}[c]
            \begin{column}{1\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=\columnwidth]{res/bluelink-standard-cores-comparison.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
        \centering
        \textit{(original table from original paper)}
    \end{frame}
    % SLIDE 8
    \begin{frame}
        \frametitle{Standardized IP Cores}
        Ethernet? Serial RapidIO? Infiniband? Interlaken? Fibre Channel? PCI Express? Altera SerialLite? Xilinx Aurora?
        \newline
        \begin{itemize}
            \item{fraught with practical difficulties: configuration constraints, fitting requirements, bonded links, manufacturer specificity, FPGA support, licensing, cost considerations}
        \end{itemize}
    \end{frame}
    % SLIDE 9
    \begin{frame}
        \begin{beamercolorbox}[center]{title}
            \textbf{BlueLink}
        \end{beamercolorbox}
    \end{frame}
    % SLIDE 9
    \begin{frame}
        \begin{columns}[c]
            \begin{column}{.75\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[height=.8\columnwidth]{res/bluelink-architecture.png}
                        \caption{architecture of BlueLink interconnect}
                        \label{fig:bluehive-architecture}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
        \centering
        basic unit of communication: 4 x 32-bit words (128-bit flit)
    \end{frame}
    % SLIDE 10
    \begin{frame}
        \frametitle{Packets}
        basic unit of communication: 4 x 32-bit words (128-bit flit)
        \newline
        \begin{itemize}
            \item{payload (64 bits)}
            \item{address (12 bits)}
            \item{CRC (32 bits)}
            \item{sequence/acknowledgement number (12 bits)}
            \item{physical layer header (8 bits)}
        \end{itemize}
    \end{frame}
    % SLIDE 11
    \begin{frame}[c]{}
        \frametitle{Application Abstractions}
        \centering
        \begin{tabular}{c}
                \fbox{Packets} \\ \\
                \fbox{Bluespec FIFO (Bluespec SystemVerilog HDL)} \\ \\
                \fbox{Remote DMA} \\ \\
                \fbox{Blocking reads and writes} \\ \\
                \fbox{Software pipes (GNU/Linux)}
        \end{tabular}
        %Content goes here
    \end{frame}
    % SLIDE 12
    \begin{frame}
        \frametitle{Results (on Stratix V)}
        \begin{tabular}{cc}
            Bandwidth
            &
            Latency
            \\                                                     
            \includegraphics[height=0.35\textheight]{res/bluelink-bandwidth.png}
            &
            \includegraphics[height=0.35\textheight]{res/bluelink-latency.png}
            \\
            \includegraphics[height=0.3\textheight]{res/bluelink-overhead.png}
            &
            \includegraphics[height=0.3\textheight]{res/bluelink-area.png}
            \\
            Overhead
            &
            Area
        \end{tabular}
    \end{frame}
    % SLIDE 13
    % SLIDE 14
    % SLIDE 15
    % SLIDE 16
    \begin{frame}[c]{}
    \centering
    \textit{Our approach shows why it is sometimes important not to simply reach for standard IP cores.}
    \newline
    \newline
    \newline
    Thank you!
    \newline
    \newline
    \newline
    Further questions?
    \newline
    \end{frame}
% etc
\end{document}
